Free Design for Testability (DFT) Analysis
and Test Coverage Report
Corelis is offering first time users a FREE,
step-by-step boundary-scan Design For Testability (DFT) analysis
of your design. We will review your design and make specific
recommendations that if implemented will improve the testability
of your board and will reduce the odds of “respinning” your
first prototype. We will also suggest improvements to your
boundary-scan design, that will board test coverage and allow
you to implement boundary-scan test and in-system programming in
a more cost-effective manner.
This FREE service also includes a test coverage report
that we recommend to do after schematic capture and before PCB
layout. At this stage of product development, Corelis will
provide you with comprehensive test coverage reports that
identify all of the boundary-scan nets and pins and classifies
them as completely tested, partially tested, or not tested. The
DFT report also recommends where to add test points (pads) for
physical "nails" access if additional test coverage is required.
We'll deliver a full report of our findings from which you will
gain immediate insights into the latest boundary-scan
techniques. Our engineers are ready to guide you through the
process on your next design.
Please complete the following form to get
This offer is not available to
companies that have previously purchased Corelis products.
Limit one per company.